1. Field of the Invention
The present invention relates to the testing of the proper fabrication of circuit components of integrated circuits with an electrical testing technique employed with a testing structure fabricated on the integrated circuit along with the fabrication of the remainder of the integrated circuit.
2. Background of the Invention
As the circuit density increases in integrated circuit fabrication, in order to attain, e.g., Very Large Scale Integration, the widths and spacings of conductors are becoming much smaller. Efficient utilization of the integrated circuit chip's "real estate" requires that both line width and spacing be the minimum possible, under the constraints of conductivity and voltage gradient requirements for efficient operation and long life and reliability. Line widths and spacings are rapidly declining into the range of a few micrometers. As they approach the orders of magnitude of the wave length of illuminating light beams used in photo processing currently employed in chip fabrication, the precision of the process tends to decline. This decline of precision becomes especially critical as the tolerances required grow smaller. This aspect of integrated circuit chip fabrication thus becomes one of the more important factors governing both design and fabrication. Measurement of conductor characteristics as actually fabricated becomes imperative. The advances in maximizing use of the chip "real estate" have made it impossible in many cases to rely solely on the precision of the photomask geometry used in fabricating the chip as is known in the art.
One approach to verifying the accuracy of the chip component sizes as fabricated is optical analysis known in the art. This requires at least several minutes of visual measurement by comparator techniques, and is not readily adaptable to automation or to high-speed production techniques. To partially overcome these drawbacks, it has previously been suggested by the applicant with others to use an electrical measuring technique employing a cross-bridge resistor, i.e., one having a van der Pauw resistor and a bridge resistor. See, Buehler, M. G., Grant, S. D., and Thurber, W. R., "Bridge and van der Pauw Sheet Resistors for Characterizing the Line Width of Conducting Layers," J. Electrochem. Soc., Vol. 125, No. 4 (April 1978), pp. 650-54, the disclosure of which is hereby incorporated by reference. This technique employed a pattern, e.g., in the form of a cross and bridge, with six larger probe pads connected to appropriate points of the structure, which was fabricated on the wafer along with other circuits as a test sample. Since this was processed along with the remainder of the circuits on the wafer, it was an accurate sample of the actual circuit conductors. By applying currents and measuring voltages to probe pads arranged in a 2 by 3 configuration, the line width and the sheet resistance of the cross-bridge resistor could be determined. The measurement was fast, and the determination of actual values from the results could be instantly accomplished by, e.g., a microprocessor or computer. Thus the cross-bridge resistor was amenable to high-speed automation techniques. However, it had at least one serious drawback in that line spacing could not be determined. Thus optical techniques were still required.
The problems enumerated in the foregoing are not intended to be exhaustive, but rather are among many which tend to impair the effectiveness of prior art techniques and apparatus for testing the fabrication of large-scale integrated circuit components. Other noteworthy problems may also exist; however, those presented above should be sufficient to demonstrate that such techniques and apparatus have not been entirely satisfactory. It is therefore a general objective of the present invention to provide an improved method and apparatus for determining the proper fabrication of components of large-scale integrated circuit chips.
3. Summary of the Invention
By fabricating a special conductor pattern on an integrated circuit, combining a van der Pauw type cross resistor, a bridge resistor, and longitudinally split-bridge resistor accessed by eight probe pads, line spacing, line width, line pitch and sheet resistance can be measured in about one second. The line pitch determination gives the measurement a self-checking capability. Thus fabrication processes can be evaluated and verified directly and quickly, as can adherence to geometrical layout rules.
A pair of conductors has been added to an extension of the cross-bridge resistor, in accordance with the present invention, with appropriate probe pads, to form a bridge resistor configuration, with the cross-bridge resistor being extended to form a longitudinally-split-bridge resistor. Each element of the split conductor is one line width wide, and they are separated by a space equalling the space width of the integrated circuit components. It is not essential that both conductors be equal. What is required is that the sum of the width of both conductors be two line widths wide. This means that the spacing feature need not be perfectly centered laterally in the split-bridge resistor. The cross and bridge resistors are preferably as wide as the sum of the three elements of the split conductor, although the cross resistor could be any size or shape of a van der Pauw construction. By use of the proper probe voltages and equations, complete measurements can be accomplished in about one second.
The present invention can be used with various integrated circuits fabricated in any of a number of ways well known in the art, e.g., deposited metal; polycrystalline silicon layers; or junction isolated diffused layers. In addition, it could be used, e.g., with printed circuit boards and with thick and thin film hybrid substrates, wherein etched metal line widths and spacing are of importance.
By calculating the line pitch, that is, the basic modular spacing of one line plus one space, in accordance with the present invention, the apparatus and method of the present invention is self-checking. If the measurements and calculations are properly made, the sum of the calculated line width and spacing must equal the designed line pitch.
With the application of the eight probes simultaneously in a 2 by 4 probe pad array in accordance with the present invention, the measurements and the calculations can be performed in about one second. These measurements are easily correlated with optical measurements, and with the photomask geometry. Thus the present invention can be used as a check on processing, for quality control in production, and for vendor evaluation. The design criteria for the structure of the present invention are explained in further detail below.
Examples of the more important features of the present invention have been summarized rather broadly in order that the detailed description thereof which follows can be better understood and the improvement in the art better appreciated. There are, of course, additional features of the present invention that will be described herein and which will form the subject of the appended claims. These other features and advantages of the present invention will become apparent from the detailed description thereof in connection with the accompanying drawings, wherein like reference numerals have been applied to like elements, and in which: